Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin

Modeling of electromigration in through-silicon-via based 3D

Abstract Electromigration (EM) is a critical problem for interconnect reliability of modern IC design, especially as the feature size becomes smaller. In 3D IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through-silicon-vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to TSV can further interact with EM and shorten the lifetime of the structure. However, there is very little study on EM issues with respect to TSV for 3D ICs. In this paper, we perform detailed and systematic studies on: (1) EM lifetime modeling of TSV structure, (2) impact of TSV stress on EM lifetime of BEOL wires, and (3) EM-robust design guidelines for TSV-based 3D ICs. Our results show EMinduced lifetime of TSV structure and neighboring wire largely depend on the TSV-induced stress. Also, lifetime of a wire can vary significantly depending on the relative position with the nearby TSV. I. Introduction As semiconductor technologies are pushed forward for higher performance with smaller power and area, threedimensional integrated circuits (3D ICs) have attracted a lot of attention from both academia and industry. 3D ICs can be realized with stacked dies and through-silicon-vias (TSVs) to communicate vertically. 3D ICs can help increase the bandwidth by reducing the interconnect length, reduce the footprint of the system, and achieve heterogeneous integration of the system. However 3D ICs introduce many new challenges, in particular the reliability issues which have become more critical. The temperature characteristics of 3D ICs can be worse, additional stress can be generated due to the coefficient of thermal expansion (CTE) mismatch between TSV and silicon materials, and current density of the interconnects needs to be increased to feed more transistors in spite of high loading capacitance of TSVs. Electromigration (EM) has been one of the major reliability problems even in conventional 2D IC designs. EM refers to the mass transport in metal structures. It is affected by geometrical shapes, temperature distribution, mechanical stress, current density, and material properties However in 3D ICs, despite of importance of EM which can shorten the lifetime of the system, only a few papers have been published regarding this issue. Shayan et al. considered mean time to failure (MTTF) due to the EM based on Black's equation, for a power distribution network (PDN) for 3D IC